The present invention relates to a method of controlling a computer system constituted by a plurality of nodes.
Recently, big data analysis is attracting attention which collects a large amount of data obtained from e-mails, SNS, web sites, sensors and the like, analyzes the data, and thereby obtaining useful knowledge. To obtain the useful knowledge in the big data analysis, it is necessary to analyze the large amount of data at a high speed.
A data center that executes the big data analysis is constructed by a storage device that stores therein the large amount of data and many servers. Inclusion of many servers enables a fast analysis of the large amount of data. Moreover, a storage device incorporating an SSD (Solid State Drive) is used to achieve a fast access to the data.
With an increase in data volume, increased speed of data analysis and improved reliability of the storage device to continue the service are required. It is also required to increase the speed of data analysis while minimizing power consumption of the data center. Moreover, there is a need of taking into account a writing life of a non-volatile storing device such as an SSD. That is, it is required to control the data center (system) so as to achieve various purposes.
Techniques described in Japanese Unexamined Patent Application Publication No. 2014-35717 and WO 2014/038073 are known to optimize processing performance, load distribution, and the like in a computer system including many computers.
Japanese Unexamined Patent Application Publication No. 2014-35717 describes, “in given three hierarchies (n to n+2 hierarchies), one node in an n+1th hierarchy obtains load information from each of one or more nodes in an n+2th hierarchy, calculates a free resource amount of its own node based on the obtained load information and the load information of its own node, and transmits the calculated free resource amount of its own node to a node in an nth hierarchy; and the node in the nth hierarchy calculates a weighted value based on the free resource amount obtained from each node in the n+1th hierarchy, and distributes a received processing request to any node in the n+1th hierarchy based on the calculated weighted value.”
Moreover, WO 2014/038073 describes, “Reliability is improved and longevity is extended in a storing device system comprising a plurality of memory modules including a non-volatile memory. For this purpose, the plurality of memory modules (STG) notify a control circuit DKCTL0 of a write data amount (Wstg) actually written to the internal write data amount. The control circuit DKCTL0 calculates an estimated write data amount (eWd) of each memory module from the write data amount (Wstg), a write data amount (Wh2d) for a write command already issued to the plurality of memory modules, and a write data amount (ntW) for the next write command. The next write command is then issued to a memory module having the least estimated write data amount.”